1. Field of the Invention
The embodiments described in the present application relate to microelectronic elements such as, for example, semiconductor chips and their manufacture. More particularly, the embodiments described herein relate to silicon-on-insulator semiconductor chips which have a guard ring for providing electrical continuity and a crack stop adjacent to the guard ring.
2. Description of Related Art
A common problem in the fabrication of microelectronic elements such as semiconductor chips is to protect the chip from cracking Semiconductor wafers are flat, thin, i.e., less than one millimeter (0.04 inch) thick, large, typically being up to 300 mm (about 12 inches) in diameter, and relatively brittle. At a final stage of fabrication, the semiconductor wafer is severed into individual semiconductor chips, either by sawing or by scribing and breaking. When severed by sawing or by scribing and breaking, the semiconductor wafer is subjected to high shear stresses which can cause cracks to form which extend inwardly from the sawn or scribed and broken edges of each chip. During use, semiconductor chips are subjected to additional stresses from heating and differential thermal expansion of the chip relative to components of packages and circuit panels to which they are attached. Due to the stresses encountered when severing the chip or even later during use, cracks can propagate inward from the edges of a chip and eventually reach an active portion of the chip, damaging semiconductor devices disposed in the active portion. To address this problem, the chip can have a crack stop in form of a metallic ring-like structure extending continuously adjacent to and parallel to the edges of the chip so as to encompass the active portion of the chip. Cracks that extend inwardly from edges of a chip are halted by the crack stop from propagating into active device areas of the chip.
The ring-like crack stop of a chip typically extends vertically upward from a monocrystalline semiconductor device layer of the chip through all of the back-end-of-line (“BEOL”) metallization layers of the chip. In some types of semiconductor chips, a crack stop has a second function to provide a conductive path to a continuous semiconductor region of the chip which serves as a common electrical ground. Typically, the continuous semiconductor region is a semiconductor region underlying the device layer of the chip which has the same predominant dopant type (either n type or p type) throughout.
One problem arises during fabrication of semiconductor chips on silicon-on-insulator (“SOI”) type wafers. SOI wafers have a structure in which a monocrystalline semiconductor device layer (usually silicon) is separated from a bulk monocrystalline semiconductor layer (also usually silicon) by a buried dielectric layer. The buried dielectric layer typically is a buried oxide (“BOX”) layer consisting essentially of silicon dioxide. In some SOI wafers, the crack stop may extend only into the monocrystalline device layer of the chip and may not connect to the bulk semiconductor region of the chip at all. This can be in order to address a manufacturing problem. A crack stop that extends continuously to the bulk semiconductor region of an SOI chip, thus grounding the crack stop, can lead to arcing during the performance of certain BEOL processing such as plasma processing and RIE. To address this problem, in some chips the crack stop extends only to the semiconductor device layer of the chip so that the crack stop is not directly connected to ground.
However, each chip needs a continuous path to ground in order to discharge high electrostatic voltages that can arise on exposed surfaces of the wafer during certain wafer fabrication processes. For example, high electrostatic voltages can arise during certain types of BEOL processing applied to a wafer to form the metal wiring lines of the chip, such as for example, during plasma and reactive ion etch (“RIE”) processes. A discharge path to ground is also needed during operation of the chip after the chip is fully completed.
Since the chip requires a conductive discharge path to ground, a ground ring can be provided separately from the crack stop for conductive connection with the bulk semiconductor region of the chip. Unlike the crack stop, the ground ring can include a contact ring which extends through the BOX layer to physically and conductively contact the bulk semiconductor region and provide a ground connection.
Thus, an SOI chip can have a crack stop formed as a series of vertically stacked continuous metal rings adjacent to the chip edges to prevent cracks from propagating from the chip edges inward towards the active portion of the chip. Such SOI chip can also have a guard ring disposed inward from the crack stop such that the guard ring and the crack stop are disposed between the active portion of the chip and the chip edges. The crack stop can be mechanically continuous in the vertical direction for stopping cracks. The guard ring extends between overlying conductive features of the chip and the bulk semiconductor region of the substrate but need not be mechanically continuous like the crack stop.
FIG. 1 is a plan view illustrating a chip 10 according to the prior art. In the various figures and views herein, features are not drawn to scale. Rather, features in each drawing are shown in a manner to enhance understanding and for ease of illustration. The chip can be a fully formed chip such as may be packaged individually and operated with a source of power applied thereto. As seen in FIG. 1, the chip includes a crack stop 11 extending in directions parallel to and adjacent to edges 20 of the chip. A guard ring 14 disposed inward from the crack stop 11 extends in directions parallel to and adjacent to the chip edges 20. An active portion 16 of the chip is disposed inward from the guard ring 14. The guard ring 14 and the crack stop 11 separate the active portion 16 of the chip in a lateral direction 15 from a peripheral portion 18 of the chip adjacent to the chip edges 20.
As seen in FIG. 1, the guard ring includes a conductive contact ring 12 which extends continuously around the active portion 16 to form a barrier laterally separating the active portion 16 from portions of the chip disposed laterally outward (i.e., closer to edges 20) from the contact ring 12. The contact ring 12 can be formed of doped polysilicon, a metal or a conductive compound of a metal. Referring to the corresponding sectional view of FIG. 2, the contact ring 12 extends vertically downward through a contact level interlevel dielectric (“ILD”) layer 21. The contact ring 12 is conductively connected to a highly doped semiconductor ring region 22 that extends downward from a major surface 24 to the bulk semiconductor region 28 of the SOI chip. The semiconductor ring region can consist essentially of monocrystalline or polycrystalline semiconductor material.
In turn, the semiconductor ring region 22 extends through the BOX layer 26 of the chip to form a conductive connection to a bulk monocrystalline semiconductor region 28 of the chip referenced as “Substrate” in FIG. 2. As seen in FIG. 2, a dielectric ILD layer 30 for a first metallization level (M1) overlies an upper surface 32 of the contact ring 12.
As further illustrated in FIG. 1, conductive pedestals 34 overlie portions of the contact ring 12 and extend vertically upward through successively higher metallization levels of the chip 10. The conductive pedestals are separated by gaps 36 in directions that the conductive contact ring 12 extends. The gaps 36 provide electrical discontinuities between conductive pedestals, preventing electrical currents from traveling laterally across the gaps between the pedestals 34.
The guard ring further includes a metallic ring 38, shown as the hatched rectangular ring area overlying all of the conductive pedestals 34 and the contact ring 12 and in conductive communication therewith. Typically provided in an uppermost (last) metallization level of the chip, the metallic ring 38 extends continuously to surround the active portion 14 of the chip. The metallic ring 38, conductive pedestals 34 and conductive contact ring 12 form conductive paths for the flow of discharge currents in a downward direction 17 (FIG. 2) to the bulk semiconductor region 28 (FIG. 2) of the chip.
The crack stop 11 includes a plurality of continuous metal rings surrounding the guard ring 14 and the active portion 16 of the chip, of which one metal ring 44 is shown in FIG. 1. Some of the metal rings of the crack stop are continuous metal lines, e.g., ring 44, in the vertically stacked wiring layers of the chip, such as M1, M2, etc. Other metal rings are provided as continuous regions of metal that connect vertically adjacent ones of the continuous metal lines.
FIG. 2 is a sectional view of the chip 10 through line 2-2′ of FIG. 1. As best seen in FIG. 2, one metal ring 44 of the crack stop 11, provided in the first metallization (M1) layer of the chip, overlies and is disposed in conductive communication with a vertically extending contact ring 46 of the crack stop. In turn, the contact ring 46 is disposed in contact with a semiconductor portion 48 of the chip 10. The semiconductor portion 48 typically consists essentially of doped monocrystalline silicon. The sectional view through line 2-2′ of FIG. 1 extends through the gap 36 between adjacent conductive pedestals 34. Therefore, the conductive pedestal does not appear in FIG. 2 and only a contact ring 12 of the ground ring, or “GR contact ring” appears which connects to an underlying GR semiconductor ring region 22. The GR ring region 22 extends through the BOX layer 26 of the SOI chip to contact the bulk semiconductor region 28 indicated as “Substrate” in FIG. 2.
An oxide isolation region 52, typically provided as a shallow trench isolation region, laterally separates the substrate ring region 22 of the guard ring from the silicon region 48 of the crack stop. In a vertical direction 17, the oxide region 52 extends upward from the BOX layer 26 to a top surface 24. The BOX layer 26 and the oxide region 52 together may form a continuous region of oxide extending upward from the bulk semiconductor region 28.
A layer 50 of silicon nitride typically overlies the top surface 24 of the dielectric region 52. The silicon nitride layer 50 typically has little to no internal stress. In chip 10, the low or zero-stress silicon nitride layer 50 functions as a barrier which inhibits or prevents the mobile ions from traveling through the layer 50. As a result, mobile ions can travel from a peripheral edge 20 of the chip through the BOX layer 26 of silicon oxide only as far as the silicon nitride layer 50. The low-stress silicon nitride layer 50 of the prior art prevents mobile ions from traveling along path 60 past the crack stop contact ring 46 and into oxide regions of the chip such as the lower ILD region 21 and the M1 ILD region 30, from where they could travel unhindered into the active device areas (not shown) of the chip.
Thus, in prior art chip 10, the silicon nitride layer 50, together with the metallic and semiconductor regions 44, 46, 48 of the crack stop form an effective barrier to prevent mobile ions from traveling in a direction from peripheral edges 20 of the chip towards an active portion 16 (FIG. 1) of the chip.